There are two webcasts coming up this thursday and friday through MSDN India that feature AMD's very own software optimization guru's, Michael Wall and Robin Maffeo. If you write native code targeted at windows apps you can't afford to miss these webcasts.

Multicore is here! But how do you resolve data bottlenecks in Native Code?
AMD's new "Barcelona" processor family is at the center of the new wave of CPU architectures. These new architectures mean new opportunities for both native and managed code. So, what opportunities do processor enhancements such as native quad-core processors, improved IPC, and L3 caches mean for your solution? This session will describe enhancements made to the Microsoft .NET Framework regarding code generation improvements and cache system pressure as a result of more cores per single chip. Developers will learn how to choose between server and workstation garbage collectors for performance, object creation tips, about lock optimizations in the CLR, and how (not) to deal with threads when developing managed code solutions. NUMA (non-uniform memory access) considerations that benefit managed code execution will also be explored. For native code development, specific Microsoft Visual C++ 2008 compiler intrinsics, compiler switches (i.e. the "/favor" flag), and other compiler and linker options will be demonstrated to enable a more informed evaluation of these options during software solution performance evaluation.

Speaker: Robin Maffeo
January 31, 2008 | 9:30PM - 11:00PM (PST)
Click here to Register

Empowering Developers: AMD x86 and x64 Performance Considerations when using Microsoft Visual Studio 2008
The industry is rushing to multi core processors. The Quad-core AMD "Barcelona" family processors, including Third Generation AMD Opteron processors and coming client offerings will integrate four complete processor cores on a single chip. In this session we will show you how to optimize your code to take advantage of these cores by feeding them with the data they require. The AMD "Barcelona" processor family implements new cache and memory features to address the data bottleneck and we will show you the basic architecture so you can successfully optimize your applications. This session will explain details of the "Barcelona" processors' innovative three-level cache system and the improved integrated memory controller. Topics include the automatic data prefetcher, L1/L2/L3 cache behavior, and explicit cache management instructions. You will learn from clear examples how to use non-temporal data, and best practices for memory and thread affinity on multi-socket "Barcelona" platforms. Take-aways includes multi-threaded code and data-parallel optimization techniques, demonstrated in C/C++ using Microsoft Visual Studio 2008.

Speaker: Michael Wall
February 01, 2008 | 9:30PM - 11:00PM (PST)
Click Here to Register

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Edited: 01/30/2008 at 01:21 AM by devcentral