Performance and stability of any system depends in part on the memory being used and the settings for the RAM timing. Many users may have their preference for "xyz" brand and certainly using brand name memory is a very good idea since low quality memory is often at the root of many stabilty issues. However, it is also important to pay attention to the timing settings of the memory being used. IMPORTANT:
Setting memory timings incorrectly could result is lost or corrupted data (resulting in system instability) or boot/post failure. If a system fails to post, default settings can be restored by clearing the CMOS/BIOS via the clear real time clock jumper on the motherboard. Refer to the board manual for the correct procedure.
The topic of memory architecture is too detailed and complex to cover in a single brief post, therefore, I will attempt to simplify a portion of the topic that adresses memory timings and how they work. Typical timing parameters look like 2-3-2-6-T1 or some other variant. So what do these numbers mean?
Before delving into these specific settings, let's first define some of the common terms used when discussing memory timings.RAS
trobe or Row Address Select. CAS
trobe or Column Address Select. tRAS
- Active to precharge delay. This is the delay between the precharge and activation of a row.tRCD
AS to C
elay. The time required between RAS and CAS access. tCL
- (or CL) C
recharge. The time required to switch from one row to the next row, i.e. switch internal memory banks.tCLK
. The length of a clock cycle.Command Rate
- This is the delay between Chip Select (CS) or when a IC is selected and the time commands can be issued to the IC.Latency
- The time between when a request is made and the request is answered. I.E, if you are in a restaurant, the latency would be the time between when you ordered your meal to the time you received it. Therefore, in memory terms, it is the total time required before data can be written to or read from the memory.
Some of the above terms are more important to system stability and performance than are others. However, it is important to understand the role of each of these settings/signals in order to understand the whole. Therefore, the numbers 2-3-2-6-T1 refer to CL-tRCD-tRP-tRAS-Command Rate and are measured in clock cycles. tRAS
Memory architecture is like a spreadsheet with row upon row and column upon column with each row being 1 bank. In order for the CPU to access memory, it must first determine which Row or Bank in the memory that is to be accessed and activate that row via the RAS signal. Once activated, the row can be accessed over and over until the data is exhausted. This is why tRAS has little effect on overall system performance but could impact system stability if set incorrectly.tRCD
There is a delay from when a row is activated to when the cell (or column) is activated via the CAS signal and data can be written to or read from a memory cell. This delay is called tRCD. When memory is accessed sequentially, the row is already active and tRCD will not have much impact. However, if memory is not accessed in a linear fashion, the current active row must be deactivated and then a new row selected/activated. It is this example where low tRCD's can improve performance. However, like any other memory timing, putting this too low for the module can result in instability. CAS Latency
Certainly, one of the most important timings is that of the CAS Latency and is also the one most people understand. Since data is often accessed sequentially (same row), the CPU only needs to select the next column in the row to get the next piece of data. In other words, CAS Latency is the delay between the CAS signal and the availability of valid data on the data pins (DQ). Therefore, the latency between column accesses (CAS), plays an important role in the perfomance of the memory. The lower the latency, the better the performance. However, the memory modules must be capable of supporting low latency settings. tRP
tRP is the time required to terminate one one Row access and begin the next row access. Another way to look at this it that tRP is the delay required between deactivating the current row and selecting the next row. Therefore, in conjunction with tRCD, the time required (or clock cycles required) to switch banks (or rows) and select the next cell for either reading, writting or refreshing is a combination of tRP and tRCD.tRAS
Next comes tRAS. This is the time required before (or delay needed) between the active and precharge commands. In other words, how long must the memory wait before the next before the next memory access can begin. tCLK
This is simply the clock used for the memory. Note that Frequency is 1/t. Therfore, if memory was running at 100Mhz, the timing of the memory would be 1/100Mhz or 10nS.Command Rate
The Command Rate is the time needed between the chip select signal and the when commands can be issued to the RAM module IC. Typically, these are either 1 clock or 2.
This covers much of the basic settings for memory and how they work. As mentioned several times in this guide, it is important to understand what timings your memory will support. Refer to you memory vendors website or datasheets to determine what settings your memory will support.
Ricjax99 has run some benchmarks that show the difference between various settings for memory timing and can be found in this thread.
Hope this helps. If you find any of the info in error or feel that I have left out any important info, please PM me and I will try to resolve.
There are 10 types of people in the world, those that understand binary and those that don't.
The opinions expressed above do not represent those of Advanced Micro Devices or any of their affiliates.
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