AMD Processors
Decrease font size
Increase font size
Topic Title: Guide to the Frontside Bus (aka FSB)
Topic Summary:
Created On: 03/24/2004 05:52 PM
Status: Read Only
Linear : Threading : Single : Branch
Search Topic Search Topic
Topic Tools Topic Tools
View similar topics View similar topics
View topic in raw text format. Print this topic.
 03/24/2004 05:52 PM
User is offline View Users Profile Print this message

Author Icon
Senior Member

Posts: 5449
Joined: 10/07/2003

The Frontside Bus – What it is, what it does

Part I – The AMD K7-platform(Athlon/Athlon XP/Duron and their respective mobile conterparts)

FSB = Front Side Bus(aka 'System Bus'
The FSB is the connection between the processor and the chipsets' Northbridge.
On a K7-platform, the memory controller is integrated into the Northbridge, so the FSB also determines your systems' memory bandwidth and I/O bandwidth since the Northbridge connects to the Southbridge and thus the rest of the system.

The CPU' core-clock is a multiple of the FSB(e.g. for an Athlon XP 3200+, 11.0(multiplier) x 200MHz(FSB) = 2200MHz(Core clockspeed)).

Now the FSB on a K7-platform is running at 100-200MHz physically. Since it is using a DDR-technology(Double Data Rate), it is capable of transferring two packets of data per clock-cycle - data is transferred on both the rising and falling edges of the clock-signal.

I___I---I___I---I = clock-signal: I---I = rising edge I___I = falling edge d = data
I___I-d-I___I-d-I SDR(single data rate, one packet of data per cycle)
I_d_I-d-I_d_I-d-I DDR

If you multiply the physical FSB clock by the number of packets that can be transferred per clock-cycle, you get the effective clockspeed - for example 133 x 2 = 266MHz

This 'effective' speed also reflects the FSBs' bandwidth which is calculated:
Effective clockspeed(in MHz) x Bus width(in bytes) = Bandwidth(in MB/s)
Physical clockspeed(in MHz) x Bus width(in bytes) x packets of data transferred per cycle(2 for DDR) = Bandwidth(in MB/s)
example: 266MHz x 8 = 2100MB/s or 133MHz x 8(64-bit) x 2(DDR) = 2100MB/s

This means a DDR'ed-bus(what the K7 is using) running at 133MHz can transfer the same amount of data per clock-cycle(i.e. it has the same bandwidth) as a SDR-Bus running at 266MHz.(single data rate, one packet per clock cycle, data is transferred on the rising edge of the clock only)

Part II – DDR-SDRAM and the K7-platform

The memory does not run twice as fast as the FSB, on the contrary, it runs at exactly the same physical clockspeed as the FSB, hence the term 'DDR-SDRAM'(Synchronous DRAM).

The key to understanding this is bandwidth. It would not make sense if the memory could deliver more data to the CPU than the FSB could handle, because it would have to wait for the CPU to receive all the data.
So the FSB runs at 133MHz, because it's DDR we get 266MHz effectively and this gets us a 2.1GB/s bandwidth.
It's exactly the same thing for the memory: it runs at 133MHz physically, uses a DDR-technology just like the FSB and thus has a 266MHz effective clockspeed which results in the same bandwidth of 2.1GB/s.
IF it were running at twice the speed of the FSB, you'd get a 4.2GB/s bandwidth, and half of it would be wasted because the FSB can only handle a maximum of 2.1GB/s.

The reason for most of the confusion about this is that people don't realize what DDR means and forget that the FSB on a K7-platform is DDR'ed.
So people say 'The CPU has a 133MHz FSB and the RAM runs at 266MHz' because they don't realize that:
1) Their FSB is DDR'ed and thus runs at 266MHz(effectively) aswell.
2) The memory is DDR'ed and runs at 133MHz(physically)

Part III – The AMD K8-platform(Athlon 64/Athlon 64 FX/Opteron and their respective mobile counterparts)

The 'classical' Frontside Bus is the connection between the CPU and the chipsets' Northbridge which contains the memory-controller and connects to the rest of the system(via the Southbridge).
If you define the FSB as the connection between the CPU and memory-controller, then it does not really exist anymore on a K8-platform since the memory-controller is integrated into the this case you could say the 'FSB' is running at full core-clockspeed.

However, if you define the FSB as the connection between the CPU and the rest of the system(regardless of whether a memory-controller is involved or not), you could say the CPUs' Hypertransport-link replaces the FSB(or it IS the FSB if you like).

The Hypertransport-link is different from a 'classical' FSB - it is not really a Bus, but a fast, packet-based point-to-point interconnect.
The HT-link comprises an upstream-(to CPU) and a downstream-part(from CPU), each 16-bits wide and clocked at 800MHz using a DDR-technology for an effective 1.6GHz clockspeed - this results in a total bandwidth of 6.4GB/s bidirectionally.

The Opteron 2xx- and 8xx-series have additional HT-links for communication between multiple CPUs.

You can find more info about Hypertransport here' ">

DDR – Double Data Rate
DDR-SDRAM – Double Data Rate Synchronous Dynamic Random Access Memory; the memory that is used in most of today's PCs
FSB – Frontside Bus
HT – Hypertransport; a fast, packet-based, point-to-point interconnect
K7 – Any AMD Athlon/Athlon XP/Athlon MP or Duron processor, including mobiles
K8 – Any AMD Athlon 64/Athlon 64 FX or Opteron processor, including mobiles
SDR – Single Data Rate

rev 1.0 – 03/24/2004

Note: The info presented above is to the best of my knowledge – if you have any questions or think some info is incorrect/inaccurate, feel free to PM me.

The opinions expressed above do not represent those of Advanced Micro Devices or any of their affiliates.

<center><font color=red>MODERATOR</center></font>

AMD Athlon 64 X2 6000+ 89W :: Asus M2N32SLI Deluxe :: 2x1024MB Muskin XP2-6400 DDR2-800 :: BeQuiet! Darkpower Pro 530W :: 2x WD Raptor 74GB/10k rpm, RAID 0 :: ATI Radeon X1950XTX
112018 users are registered to the AMD Processors forum.
There are currently 0 users logged in.

FuseTalk Hosting Executive Plan v3.2 - © 1999-2014 FuseTalk Inc. All rights reserved.

Contact AMD Terms and Conditions ©2007 Advanced Micro Devices, Inc. Privacy Trademark information