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Topic Title: Core i7
Topic Summary: pwnage...
Created On: 11/08/2008 01:46 AM
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 11/09/2008 05:58 PM
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MU_Engineer
Dr. Mu

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Originally posted by: Athlonuser

When I look back...I think Intel was kicking back and letting AMD pull ahead back in the P4 days.


I don't think so. Intel's goal back then was to transition people from x86 to Itanium, where they could cut out the x86 legacy cruft, enable 64-bit operation, and probably the most importantly, be the unambiguous sole licensor of the ISA and force AMD, VIA, Transmeta, and National Semiconductor to make their own incompatible ISA and compete against Intel (which would likely result in Intel having all but a percent or two of the desktop market.)

Three things derailed those plans. One was the Itanium being delayed from an originally-anticipated 1998 launch to a 2000 launch, which meant that it fared poorly versus the 64-bit RISC processors in the big iron servers on introduction and failed to gain much of a foothold. The second was AMD launching the K8 with a 64-bit ISA that was backwards-compatible with the current x86 ISA. And the third was Intel running into thermal issues with the P4 line. Intel most likely originally intended for their desktop CPU progression to go PIII Katmai -> PIII Coppermine -> P4 Willamette -> P4 Northwood -> Itaium 2, but they ran into issues with their new 180 nm process with the Coppermine (delays in getting the chips made, then scaling issues) and that set them back a ways. Intel also goofed with the P4 Willamette's socket 423 and RDRAM as well, which set them back a bit and delayed Itanium development and Itanium uptake. They finally got things sorted out with the P4 Northwood but they originally intended to take it well above the 3.4 GHz the fastest Northwood shipped at.

AMD introducing the Opteron in 2003 with the x86_64 ISA in the face of Intel not being able to run up the clock speeds on Northwood-based Xeons (Prestonia/Gallatin) made the market much more receptive to using AMD's parts rather than avoiding them in favor of Intel's Itanium. The good uptake of the Opteron and the dead-end of the NetBurst clock speed ramp pretty much kiboshed the plans for Intel to establish the Itanium IA64 as the next de facto standard ISA. Intel also made a tremendous flop with the P4 Prescott and their "next big thing" of the third-generation NetBurst Tejas and Jawhawk CPUs having an even worse thermal envelope than Prescott made Intel stumble and scramble to come up with a new ISA. Fortunately they had the Israelis working on modified PIIIs (Pentium M, Core Solo/Duo) to pull their fat out of the fire on that one and provide them with the bones of their current Core 2 processors.

I don't think AMD is going to have a chip that takes names and/or pwns anytime soon.


I wouldn't say that. AMD's current processors are reasonably competitive with the Core 2s at similar clock speeds- it's just the fact that Intel executed 45 nm well and gotten ahead in the process node department that let them ramp up clock speeds well above what AMD could manage with 65 nm. The QX6700 isn't that much faster than the Phenom X4 9950BE and it has a pretty similar TDP. Intel did get to 3.00 GHz on 65 nm with quads and AMD could have sold ~3 GHz Phenom X4 Agenas if they could have commanded >$1000 for them like Intel did with the QX6800 since both are very high-binned chips.

I wouldn't count AMD out anytime soon. Supposedly the 45 nm transition has been going well for them and the Agenas are fundamentally sound in their design- they could just use some more cache and clock speed and a little bit more friendly thermals. The Deneb is exactly that- three times the L3 cache size and up to 400 MHz more clock speed and with a lower TDP.

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 11/09/2008 08:23 PM
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Firestrider
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MU_engineer do you know what step size is when regarding the memory hierarchy?

I looked at some comparisons of Core i7 to K10 and it seems Intel has a lower latency L3 cache and main memory when the step size is greater than 64.

Core i7 also has higher bandwidth in all levels of cache.
 11/09/2008 10:37 PM
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MU_Engineer
Dr. Mu

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I believe in that case the step size is the size of contiguous blocks of memory in bits they grab from memory. I'd imagine that the Core i7 would be faster at getting more than one 64-bit cache line in a sequential read from memory at one time since it has a ganged 192-bit IMC versus the two independent/unganged IMCs in the K10. Also, DDR3-1333 or -1600 or whatever they were using has a lot more bandwidth per channel than the DDR2-800 everybody seems to test Phenoms with, which would also cause a result in favor of the i7.

EDIT: Also, remember that the L1 and L2 cache run at core speed. A 3.2 GHz Core i7 965EE will have a lot more L1 and L2 cache bandwidth and lower latency than a 2.6 GHz Phenom X4 9950 BE since the i7's caches are operating at 600 MHz higher speed.

Synthetic benchmarks are an academic curiosity, but far too many people put far too much importance on them. For example, the P4 did very well in many synthetic benches but we know how well they performed in real-life situations.

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 11/10/2008 01:06 AM
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PorscheRacer14
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EDIT: Also, remember that the L1 and L2 cache run at core speed. A 3.2 GHz Core i7 965EE will have a lot more L1 and L2 cache bandwidth and lower latency than a 2.6 GHz Phenom X4 9950 BE since the i7's caches are operating at 600 MHz higher speed.


Just from overclocking my FX-60 from it's stock 2.6GHz to 3GHz, I can drop the L1 latency by almost 5ms. So yes, 600MHz means probably a huge difference in latency. And I do agree with you on why they never seem to benchmark the Phenoms with 1066MHz RAM with tight latencies. That's how I setup my pals quad-core 790FX Spider system and my parents780G tri-core system. It made a huge difference changing it from 800MHz to 1066MHz and setting it to ganged mode.

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 11/10/2008 05:40 AM
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brane212
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Is there any useful data on Phenom's L3 cache latency ?

AFAIK L3 should feature variable latency, depending on momentary cache load, but it would be nice to know all variables fo that equation...

Also, since L3 runs on the Memory controller clock, it woould be nice to know what parameter to tweak in BIOS to lift that clock.

Is it related to RAM frequency CLK ?
 11/10/2008 06:37 AM
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PorscheRacer14
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On the Phenoms it's the Northbridge to HT Link Speed clock that you would adjust in the BIOS. Or at lest adjusting that setting seems to make the most improvements even more so than overclocking the HT Clock (or memory clock, same thing). I could be wrong on this, but that makes the most sense to me in what you are asking about. I should probably look more into this since these new methods are the way of the present and future, the Athlons and FSBs of the past are now put out to pasture along with Windows For Workgroups 3.11 embedded licensing which retired last week after 15 years.

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 11/10/2008 09:18 AM
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piotter1988
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Lol does anyone else see a problem in this

Three channel memory: each channel can support one or two DDR3 DIMMs. Motherboards for Core i7 have four (3+1) or six DIMM slots instead of two or four, and DIMMs should be installed in sets of three, not two.


it seems they're being supremely intelligent... or not,
even intels 1st X58 board has 4 slots...
do they know something they aren't telling anyone?

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 11/11/2008 01:18 AM
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Overmind
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Originally posted by: MU_Engineer

I'll wait for the full release where we see it benched on something other than a couple of Windows synthetic benchmark programs, games, and Cinebench to make my judgment. This really reminds me of the "OMG PWNAGE!!!!" threads that sprung up after Intel leaked Core 2 Duos to reviewers and they ran SuperPi and integer/SSE synthetic benchmarks. The actual units were not nearly that much faster in relation to the K8s than those cherry-picked benches showed. Or the 45 nm C2D tests where everybody ran alpha builds of video encoding software with SSE4.1 support to get a "ZOMG IT PNWS J00!!" result but the chips were a few percent faster than the Conroes.

That's true.
But the new intels look very solid (except for the memory part).
It's a new architecture design that even comes with the old HyperThreading cheat.
It's gonna be very difficult to beat.

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 11/11/2008 03:37 AM
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Raqia
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I'm most excited about AMD's (supposedly) solid execution this time around. They need to improve their revenue stream so they can invest more in R&D and this is a good step in that direction after the Barcelona fiasco. Dirk Meyer should also be a much more realistic CEO since he has a very strong engineering background and point AMD in good general directions.
AMD Processors » AMD Enthusiast Community » General Technology Chat » Core i7

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