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Topic Title: Compatibility of AMD and Intel CPUs when 'mfence' instruction is used
Topic Summary: Compatibility of AMD and Intel CPUs when 'mfence' instruction is used
Created On: 08/31/2012 12:17 AM
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 08/31/2012 12:17 AM
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SergeyKostrov
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Joined: 08/28/2012

I'm a C++ Software Developer and my question is related to compatibility of AMD and Intel CPUs when 'mfence' instruction is used in an application designed and implemented for Intel CPUs in the first place.

I've read that some older AMD CPUs do not support that instruction. Is that correct?

Could you provide as much as possible information on which AMD CPUs did not support 'mfence' instruction? How many years ago was it?

Are there any references I could look at on AMD web-site, like links to docs, C++ or ASM examples?

Could you provide some tips for implementing programming solutions on older AMD CPUs when 'mfence' instruction is not supported.

Best regards,

Sergey

 

 09/14/2012 12:13 PM
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Blazorthon
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Joined: 09/14/2012

If I had to guess, I'd say that Athlon 64 and up probably support the instruction that you're asking about. I can only give a probably, but it's something. I tried a web search, this is what I found, and maybe it will help:

https://lkml.org/lkml/2008/1/2/350

https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences

http://en.wikipedia.org/wiki/Memory_ordering

From what I can tell, even though at least since Athlon and Phenom, AMD did support this instruction (probably even earlier too), but it's not ideal on their CPUs. Maybe if AMD's CPU/NB frequency is brought up significantly, it'd work better.

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