Originally posted by: a.green
Is there any compatibility considerations about mixed opteron and xeon cluster? I mean if I compile my source code in opteron 64 bit (using gcc), will the binary work on xeon?
Whether or not the binary runs depends on what you use in your CFLAGS and CXXFLAGS. The thing you don't want to do is have a binary compiled with SIMD extensions that one of the chips cannot execute. For example, using "-msse4a" or "-march=barcelona" in your flags may lead to the Xeons segfaulting on an "illegal instruction" error as no Intel CPU supports all of the SSE4A instructions. Likewise, no current Opteron can run all of the instructions in Intel's SSSE3, SSE4.1, SSE4.2, or AVX instruction sets, so any flag that calls them (including the "-march" flags for Core 2 and Core i7 CPUs) may cause segfaults on AMD CPUs. If in doubt, don't set the -march and don't use any -msse* flags. You can use -msse3 if you are running dual-core or greater Opterons since all 64-bit Xeons and dual-core or later Opterons support SSE3. Past SSE3, the SIMD instructions AMD and Intel CPUs support vary. AMD is supposed to be adding support for most of Intel's SIMD instructions in Bulldozer, but that's not shipped yet.