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Topic Title: Athlon64 Venice / San Diego and mismatched DIMM's
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Created On: 07/15/2005 10:39 AM
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 07/15/2005 10:39 AM
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JAT
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Posts: 45
Joined: 07/15/2005

So like. http://techreport.com/reviews/...thlo...ce/index.x?pg=1' ">http://techreport.com/reviews/...64-venice/index.x?pg=1 says that there are following improvement at Athlon64 Venice-processors:

"Support for mismatched DIMM sizes per channel — The memory controller built into the Athlon 64 has been tweaked to allow for DIMMs of two different sizes to coexist in a single memory channel. That means it would be possible, in a Socket 939 system with two memory channels, to plug in two pairs of DIMMs that are different sizes without gravely compromising performance. "

So they say, that you can put for example 256+256 and 512+512 memory sticks and ít should work. As far as I know, this coimbination works with older processors also if there are same amount of memory on each channel.

So I'm asking following:

1. Is it possible, when using Venice/San Diego-core processor, to have different amount of memory on channels assuming that at least 3 DIMM slots of 4 are populated. For example, does combination of 3 512 MB DIMM's work? As far as I know, it doesn't even with Venice-processors.

2. Does the statement above mean, that Venice-processor IS REQUIRED to use 2 pairs of different amounts of memory. For example

Channel 1: 512 + 256
Channel 2: 512 + 256

As far as I know, that combination should work with Clawhammer processors also.

3. Or does the following statement "to plug in two pairs of DIMMs that are different sizes without gravely compromising performance." mean, that whis combination will work without any performance hit with Venice processors but using it with Clawhammer will result in some performance hit. Just like using 4 DIMM's with Clawhammer processors will cause some performance decrease but if you use Venice, that should not happen.

Thanks to everyone, who can say something useful.

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http://www.jathardware.com' ">http://www.jathardware.com
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