AMD Processors
Decrease font size
Increase font size
Topic Title: Remote Memory access
Topic Summary:
Created On: 02/08/2005 10:59 PM
Status: Read Only
Linear : Threading : Single : Branch
Search Topic Search Topic
Topic Tools Topic Tools
View similar topics View similar topics
View topic in raw text format. Print this topic.
 02/08/2005 10:59 PM
User is offline View Users Profile Print this message

Author Icon
jjahir
Junior Member

Posts: 13
Joined: 12/20/2004

Incase of 4 processor AMD opteron architecture, what will happen if 3 processors made remote memory request on a single node at the same time.

How the cross bar of the requested CPU handle the memory requests from all nodes if it happen at the same time ?

whether any bus contention happen ?

What is the purpose of having 3 hypertransport channels. ?

regards
JahirHussain
 02/09/2005 08:05 AM
User is offline View Users Profile Print this message

Author Icon
OrangesAway
Senior Member

Posts: 202
Joined: 03/09/2004

It's not a bus, so there is no bus contention in that sense. Hypertransport is essentially a point to point connection.

The XBAR has a number of buffers, as described in section 3.6.8 of the BIOS and Kernel Developer's Guide for AMD Athlon™ 64 and AMD Opteron™ Processors' ">http://www.amd.com/us-en/asset...nd_tech_docs/26094.PDF document:

QUOTE
3.6.8 XBAR Flow Control Buffers
The Northbridge interfaces with the CPU core, DRAM controller, and, through three HyperTransport links, to external chips. The major Northbridge blocks are: System Request Interface (SRI), Memory Controller (MCT), and Cross Bar (XBAR). SRI interfaces with the CPU core and connects coherent HyperTransport links and noncoherent HyperTransport links. MCT maintains cache coherency and interfaces with the DRAM. XBAR is a five port switch which routes the command packets between SRI, MCT, and the three HyperTransport links. Not all HyperTransport links have to be active.

The number of buffers available for each link at the XBAR input is shown in Table 23.


Not all AMD K8 processors have 3 HT (Athlon 64 and Athlon 64-FX do not, they have only 1. The purpose of 3 connections is to allow multi-processor configurations or multiple high-speed connections to other chipsets.
Statistics
112018 users are registered to the AMD Processors forum.
There are currently 0 users logged in.

FuseTalk Hosting Executive Plan v3.2 - © 1999-2014 FuseTalk Inc. All rights reserved.



Contact AMD Terms and Conditions ©2007 Advanced Micro Devices, Inc. Privacy Trademark information