It's not a bus, so there is no bus contention in that sense. Hypertransport is essentially a point to point connection.
The XBAR has a number of buffers, as described in section 3.6.8 of the BIOS and Kernel Developer's Guide for AMD Athlon™ 64 and AMD Opteron™ Processors
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3.6.8 XBAR Flow Control Buffers
The Northbridge interfaces with the CPU core, DRAM controller, and, through three HyperTransport links, to external chips. The major Northbridge blocks are: System Request Interface (SRI), Memory Controller (MCT), and Cross Bar (XBAR). SRI interfaces with the CPU core and connects coherent HyperTransport links and noncoherent HyperTransport links. MCT maintains cache coherency and interfaces with the DRAM. XBAR is a five port switch which routes the command packets between SRI, MCT, and the three HyperTransport links. Not all HyperTransport links have to be active.
The number of buffers available for each link at the XBAR input is shown in Table 23.
Not all AMD K8 processors have 3 HT (Athlon 64 and Athlon 64-FX do not, they have only 1. The purpose of 3 connections is to allow multi-processor configurations or multiple high-speed connections to other chipsets.