Hello!

I’m wondering if anybody knows the replacement policies for the translation look-aside buffer used in the Opteron core?

I’m guessing it's implemented to reduce the numbers of page fault rather than reducing the I/O. But I can't find any whitepapers on this....


And another question while I'm at it:

Anybody knows how, exactly, the TLB-filter, patented by AMD, works? And witch type of unnecessary TLB flushes does it stop?

Thanks
/Erik Åkerfeldt, student at KTH

The patent is readable here, US Patent 6,453,387' ">http://patft.uspto.gov/netacgi.../6453387&RS=PN/6453387 which seems to imply by LRU in the title.

You might have better luck if you 'google' for check CiteSeer for both the old name Hammer as well as the new Opteron and AMD64 as I think there more more disclosures under the code name than the released one.

Couple of basic places to get started:

Nice write-up by Chip-Architect on the Opteron Core at Understanding the detailed Architecture of AMD's 64 bit Core (See section 3.3)

Some of the MPF documentation on Hammer from the old days: 2001 Hammer MPF' ">http://www.amd.com/us-en/asset...ammer_Presentation.PDF

Can also check some of the architecture manuals, like AMD64 Architecture Vol2 System Programming' ">http://www.amd.com/us-en/asset...nd_tech_docs/24593.pdf (See section 5.5)

Not sure any of them will give you easy read of the replacement algorithim itself -- But there is a good description of the TLB function and maybe you can infer the replacement algorithim.

Tanks!

The “understanding the detailed architecture of AMD’s 64 bit core”, good and with dense information, has no reference – it’s just simple signed “hans”. It’s good for an overview but I can not use such recourses for scientific research.

The fist link was great! It was pretty much the one I was looking for!

Tanks!
/Erik

Just to give credit where it is due, I got the patent link from the Chip Architect site, which is great. In March 2003, by looking at Prescott core's and "counting pixels", he predicted the 64 bit extensions from Intel.