If you compare the PCI Express x16 graphics implementation of the new VIA K8T890 chipset with the upcoming Intel 925XE chipset:


VS.


Some argue that for I/O<->RAM communication can occur directly within the Intel 925XE chipset without saturating the FSB, but for the VIA K8T890 chipset this communication can't go directly and instead like I/O<->CPU<->RAM and thus saturatin the HyperTransport bus. They even go as far as saying that the bandwidth of the 1GHz HyperTransport bus and the memory controller bus represent a bottleneck for the VIA K8T890 chipset with regards to the PCI Express implementation.

I thought that for I/O<->RAM communications, the CPU only worked like a crossbar so that communication can occur directly without saturating the HyperTransport bus at all, or do I have it all wrong?

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My [i' ">http://forums.amd.com/index.php?showtopic=2208 8^)

I/O to RAM still does not happen direclty in the intel chipset, as the chipset is also a step in the middle, the same as a traditional K7 Northbridge.

On hypertransport, yes the I/O has to go into the CPU first, but it's not going into the CPU core, instead it is directly routed to memory via the highspeed crossbar inside the CPU.

This means there is minimal latency (no more then a traditional northbridge has on I/O data)
It also means it doesn't increase CPU load when transfering I/O to memory (same as a traditional northbridge)

As far as Hypertransport at 1Ghz being a bottle neck, it has 8GB/s on bandwidth, 4GB in each direction at the same time.

That is exactly as much bandwidth as PCI-Express x16, so could handle the PCI-express running at full speed non-stop.
It would not be a bottle neck for a very long time.

Also take into account that hypertransport 2.0 can run up to 22.4GB/s, there there is lots of room for the future.

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' ">http://www.ZapWizard.com
The opinions expressed above do not represent the views of Advanced Micro Devices or any of their affiliates.

So what's correct then:

1.

w/DMA:

Intel: PCI-E x16 gfx<->82925X<->RAM (2 hop)
VIA: PCI-E x16 gfx<->K8T890<->RAM (2 hop)

w/o DMA:

Intel: PCI-E x16 gfx<->82925X<-FSB->CPU<-FSB->82925X<->RAM (4 hop)
VIA: PCI-E x16 gfx<->K8T890<-HTT Xbar->CPU/RAM (2 hop)

or this

2.

w/DMA:

Intel: PCI-E x16 gfx<->82925X<->RAM (2 hop)
VIA: PCI-E x16 gfx<->K8T890<-HTT Xbar->RAM (3 hop)

w/o DMA:

Intel: PCI-E x16 gfx<->82925X<-FSB->CPU<-FSB->82925X<->RAM (4 hop)
VIA: PCI-E x16 gfx<->K8T890<-HTT Xbar->CPU/RAM (2 hop)

The confusion is if the HyperTransport (HTT) crossbar (Xbar) is being utilized even with DMA transfers over the PCI Express bus?

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My [i' ">http://forums.amd.com/index.php?showtopic=2208 8^)