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Topic Title: K6-2 Front side bus latency
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Created On: 11/12/2004 12:08 AM
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 11/12/2004 12:08 AM
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36teeth
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Joined: 11/11/2004

Hello,
I'm writing an embedded OS for a device with K6-2 processor, and I can't find information about memory latency. For instance, i wrote in my program
mov eax,[ebx].
L1 cache do not contain with required data, sothis instruction will delay for sometime. if my memory have timing model X-Y-Y-Y(actually 7-2-2-2 or 7-1-1-1), and processor have multiplier N(actually 5), how many clocks will pass until data will be available in L1? In another words, how many clocks it will take to start reading from memory? and how mush clocks will pass between moment when 8bytes arrive to processor and moment when these bytes will be in eax?

thanks. dmitry/
 11/12/2004 07:31 AM
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KachiWachi
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Joined: 06/11/2004

Aren't these chipset parameters?

Have you looked in the AMD CPU datasheet for this information?

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 11/12/2004 06:43 PM
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36teeth
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Joined: 11/11/2004

There were no information about latency at all.
I've done some tests,but I can't believe that results are correct
when reading memory with 64byte step,latency per cycle is 0 for L1(it's OK). But When block size exceeds L1, latency is about 100 clc. K6 automaticaly prefetches 2 row, but prefetch time for L2 is 5*2*(3+1+1+1)=60 clc. What is happening during last 40 clc?
 11/13/2004 07:55 PM
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Wildcard
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Joined: 02/14/2004

Hi there,

You say you're writing an entire OS in assembler for it? Wish I could do that..

The K6-2 has no L2 cache, you have to use a K6-2+ or K6-III+ with 128/256K L2 cache running at clock speed, to lower those latencies. This cache is shared between instructions & data.

If your optimised code routinely breaks the cache barrier despite burst operations and fast FSB speeds, and latency is mission-critical, you would have to use one of the + chips or an alternative processor altogether. I am not sure whether or not you could benefit from the "3DNow!" SIMD instruction extensions at your disposal.

Sorry if this is a bit vague, I'm still trying to get round your numbers. Would CPU-Z help bench test your theory for you? Also, would it be that partity checking of both cache and memory is adding to the delays you're encountering?


CPU-Z Latency Results for an overclocked Duron1800

Air cooling and 1.58v core.



Duron's have 128kbyte L1 cache & 64Kbyte L2 (Athlon's have 256k or 512k L2).


Memory Timings For The Avove Tests

166 FSB: 2-3-3-7CL

CAS: 2
RAS to CAS: 3
RAS Precharge: 3
Tras: 7


200 FSB: 2.5-4-4-8CL

CAS: 2.5
RAS to CAS: 4
RAS Precharge: 4
Tras: 8


Links

CPU-Z http://www.cpuid.com' ">http://www.cpuid.com

K6-x+ CPU Info http://www.redhill.net.au/c-6.html' ">http://www.redhill.net.au/c-6.html

Misc K6 documentation from AMD http://www.amd.com/us-en/Proce...oduc...88^1102,00.html' ">http://www.amd.com/us-en/Proce...1260_1288^1102,00.html

-------------------------
. AMD CPU Data: http://www.tomshardware.com/20.../amd...ult/page23.html & http://www.amdboard.com/amdid.html
. Belarc Advisor: http://www.belarc.com/free_download.html
. GPU Comparison for Laptops: <a href="http://www.notebookche
 11/14/2004 07:20 AM
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KachiWachi
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My DFI board, just for comparison -

Cache latency computation, ver 1.0 (CPU-Z 1.24)

size (Kb) stride 4 8 16 32 64 128 256 512
1: 2 2 2 2 2 2 2 2
2: 2 2 2 2 2 2 2 2
4: 2 2 2 2 2 2 2 2
8: 2 2 2 2 2 2 2 2
16: 2 2 2 2 2 2 2 2
32: 2 2 2 2 2 2 2 2
64: 2 3 6 12 24 24 24 24
128: 2 3 6 12 21 18 18 17
256: 7 15 30 60 119 121 121 120
512: 9 16 32 64 129 131 130 130
1024: 9 17 35 70 140 141 141 142
2048: 9 18 38 77 153 154 154 154
4096: 9 18 38 80 160 161 160 160
8192: 9 18 39 81 162 161 161 161
16384: 9 18 39 81 162 161 161 161
32768: 9 19 39 80 162 161 161 161

2 cache levels detected
Level 1 size = 32Kb latency = 2 cycles
Level 2 size = 128Kb latency = 20 cycles

K6-2/+ 450 (@6x66MHz for 400MHz), 60nS EDO, 6-2-2-2 timings (3-1-1-1-1-1-1-1 via L3 cache)

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 11/14/2004 07:37 AM
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KachiWachi
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Joined: 06/11/2004

Results using CacheMem (it posts results for the entire system) -

Summary - K6-2+/450MHz (6x66MHz for 400MHz)
Latency (CPU Clocks): 2/23/72/166
Latency (Bus Corrected): 2/23/12/27.5
L1 cache (32KB) speed (MB/s): Read=3033.7, Write=3033.7
L2 cache (128KB) speed (MB/s): Read=1520.2, Write=1013.5
L3 cache (512KB) speed (MB/s): Read=336.5, Write=146.8
Main memory speed (MB/s): Read=144.2, Write=70.1

*Note* - Latencies above are L1, L2, L3, RAM

Cache size/Memory speed info tool 2.65MMX - © 1999-2001, LRMS - DJGPP compiled
CPUID support detected... 'AuthenticAMD' with FPU TSC MMX
Family=5 Model=13 Step=4 Type=0 Chipset (Vendor/Device ID(Rev)): Intel/7030(02)
CPU clock: 398.9 MHz
Using 32MB physical memory block (alignment = 32)

Bandwidth - MMX linear access test... Read/Write/Copy (MB/s)
Block of 1KB: 3042.5 / 3042.4 / 4645.4
Block of 2KB: 2972.8 / 2972.9 / 4790.3
Block of 4KB: 3007.3 / 3007.2 / 4807.1
Block of 8KB: 3024.9 / 3024.9 / 4829.0
Block of 16KB: 3033.7 / 3033.7 / 4368.6
Block of 32KB: 2987.7 / 2941.1 / 1011.3
Block of 64KB: 1520.2 / 1013.5 / 999.5
Block of 128KB: 1506.9 / 1007.2 / 218.2
Block of 256KB: 336.5 / 146.8 / 218.2
Block of 512KB: 336.4 / 146.8 / 118.2
Block of 1024KB: 181.6 / 84.2 / 110.8
Block of 2048KB: 159.5 / 76.0 / 104.4
Block of 4096KB: 150.4 / 72.5 / 101.4
Block of 8192KB: 146.2 / 70.8 / 100.0
Block of 16384KB: 144.2 / 70.1 / 99.4
Block of 32768KB: 143.3 / 69.7

Latency - Memory walk tests... ("pointer chasing")
Null size: 2 cycles 1 cycles (overhead 41 cycles)
steps: 4 8 16 32 64 128 256 512 1k 2k 4k (bytes)
Block of 1KB: 2 2 2 2 2 2 2 2 - - - cycles
Block of 2KB: 1 2 2 2 2 2 2 2 2 - - cycles
Block of 4KB: 1 2 2 2 2 2 2 2 2 2 - cycles
Block of 8KB: 1 2 2 2 2 2 2 2 2 2 2 cycles
Block of 16KB: 1 2 2 2 2 2 2 2 2 2 2 cycles
Block of 32KB: 1 2 2 2 2 2 2 2 2 2 2 cycles
Block of 64KB: 2 3 6 12 24 24 23 23 23 23 23 cycles
Block of 128KB: 3 3 6 12 23 23 22 23 23 23 23 cycles
Block of 256KB: 6 9 18 36 72 72 72 72 72 72 72 cycles
Block of 512KB: 9 9 18 36 72 72 72 72 72 72 72 cycles
Block of 1024KB: 13 21 42 73 106 126 133 133 133 133 134 cycles
Block of 2048KB: 12 21 43 72 105 149 147 150 151 152 152 cycles
Block of 4096KB: 12 21 42 74 107 149 155 159 161 161 161 cycles
Block of 8192KB: 14 21 42 74 107 149 163 163 165 165 166 cycles
Block of 16384KB: 15 21 42 74 107 149 163 167 167 168 168 cycles
Block of 32768KB: 15 21 42 74 107 149 163 167 169 169 169 cycles
This system appears to have 3 cache levels (enabled).
L1 cache (32KB) speed (MB/s): Read=3033.7, Write=3033.7
L2 cache (128KB) speed (MB/s): Read=1520.2, Write=1013.5
L3 cache (512KB) speed (MB/s): Read=336.5, Write=146.8
Main memory speed (MB/s): Read=144.2, Write=70.1

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 11/14/2004 12:26 PM
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bvchurch
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Joined: 06/24/2004

You could always just contact AMD.
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