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Topic Title: Athlon 200MHZ FSB questions
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Created On: 05/03/2004 12:41 PM
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 05/03/2004 12:41 PM
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Joined: 05/03/2004

Hello Everyone,

Got two quick questions that I've been searching on the net and can't find the answers to, here they are:

1. What corporation did Advanced Micro Devices team up with to develop its 200-MHz AMD Athlon system bus interface?

2. What was the name of the original system bus architecture that the Athlon bus interface was modeled after?

I've been doing a research paper on AMDs new 64 bit chips and my instructor nailed me with these two questions. Any help or resources where I can find these answers would be very much appreciated! Thank you,

 05/03/2004 04:04 PM
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MD - Moderator
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#1.Compaq alpha.
#2. EV6 bus, but it is dropped for the NUMA based bus in the Hammer core.

From the web...
The EV6 bus operates only between the CPU and the chipset. This allows a very high speed data pipe to be established between the processor and core logic. The EV6 DOES NOT talk directly to the memory, but instead leaves this up to the chipset. The upshot of this is that a 200 MHz bus can be run with PC 100 SDRAM as the memory bus is independent from the processor bus. The K7 will also see separate buses for AGP and and PCI.
This means that the K7 can be run with a wide variety memory types including:

* PC 100 SDRAM. The current high volume manufactured memory.
* RDRAM aka RAMBUS, can run up to speeds of 800 MHz, but is currently very costly to manufacture.
* DDR SDRAM meaning Double Rate SDRAM. Can achieve RDRAM levels of performance at 100 MHz. Works in way similar to AGP 2X.

This allows a high degree of flexibility in configuring K7 based systems, especially as AMD is in a position where it can only re-act to the memory market and does not lead it. Very clever design indeed.

This EV6 bus will be especially useful for high end server and workstation machines as it implements "point to point" topology allowing CPU's to establish an independent link to the chipset. This of course is only of use in multi-processor systems but is a huge advantage over GTL+ in that each chip has its own connection to the chipset, whereas under GTL+ each processor must share one single connection. This allows up to 16 K7's to be run in a multi-processor system.



The opinions expressed above do not represent those of Advanced Micro Devices or any of their affiliates.

Physics? Ha! This is clearly magic and devilry at work. Prepare firewood! We have witches to burn!

 05/04/2004 12:08 AM
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Thanks a lot!

I didn't think that I'd get a reponse that quick! Have a good one,

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