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Topic Title: Cpumark99 on K6-2/3
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Created On: 07/13/2004 05:29 PM
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 07/15/2004 09:40 PM
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KachiWachi
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For example -

Refresh Command Delay 9 8 7 *6*

6 what...clocks, seconds, meatballs, etc...??

You can turn off the virus protection...your AV should have that covered.
We spoke about the BIOS shadows in the other post too...

What are the default settings for the "hidden" items?

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 07/15/2004 10:31 PM
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Charlie22911
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ive edited every thing to look like they do in the bios,I'm sorry but i don't know what they mean either,i just posted them the way they looked in the bios,i doesn't tell me what they mean ...
I'm so sorry but Ive lost where you posted that about the shadowing ,Ive been a little off for some reason,probably the cake ,so which is better cached shadowed or disabled .just curious does that chip away virus do anything,and could that be what is helping my system slow down?


Charlie.

-------------------------
Desktop:
Phenom II x6 1055T @ 4GHz | 4x2GB Patriot DDR3 1600 @ 2000 | 3x AMD Radeon HD6970 Crossfire

Laptop:
Core i7 2960xm @ 4.2Ghz | 4x4GB Kingston DDR3 1866 | 2x GTX 580m SLI OC 725/1450/1500
 07/16/2004 06:57 AM
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KachiWachi
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The ChipAway provides HD boot block write protection from viruses. Most AV programs provide this function now, so you don't need to run this in the BIOS too.

As for the cache settings, we had mentioned that there really is no longer a need to enable those, since they "steal" valuable cache lines.

I still need to know what the "F6" and "F7" values are for the functions on the Advanced Setup page. Perhaps a photo would be easier, but typing them is OK too. Post back when you can, and I'll look into the "meatballs".

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 07/16/2004 06:47 PM
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Charlie22911
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photos are a no go because i don't have a camera since I'm at home now (I'm baffled at why my dial up still works )the most i can do is type.
will let you know what comes up .


Charlie

-------------------------
Desktop:
Phenom II x6 1055T @ 4GHz | 4x2GB Patriot DDR3 1600 @ 2000 | 3x AMD Radeon HD6970 Crossfire

Laptop:
Core i7 2960xm @ 4.2Ghz | 4x4GB Kingston DDR3 1866 | 2x GTX 580m SLI OC 725/1450/1500
 07/16/2004 11:42 PM
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Charlie22911
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ok got the results:

_________________________
optimal preformance values:

Refresh Command Delay-6
RAS Precharge Time-5
RAS to CAS Delay-4
Refresh Queue Depth-12
CAS Latency-3
Inital Latency Timer-32

best preformance values:

Refresh Command Delay-8
RAS Precharge Time-2
RAS to CAS Delay-2
Refresh Queue Depth-12
CAS Latency-2
Inital Latency Timer-16
---------------------------------

my computer hanges when it identifies the drives with best preformance loded.
also something i just noticed is when i choose to "shut down" my computer it simply restarts as if i chose that command,ITS GETTING ON MY NERVES,why does it do that?

-------------------------
Desktop:
Phenom II x6 1055T @ 4GHz | 4x2GB Patriot DDR3 1600 @ 2000 | 3x AMD Radeon HD6970 Crossfire

Laptop:
Core i7 2960xm @ 4.2Ghz | 4x4GB Kingston DDR3 1866 | 2x GTX 580m SLI OC 725/1450/1500
 07/17/2004 08:21 AM
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KachiWachi
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Thanks Charlie...I'll take a look.

Windows Shutdown issues on 98 have been around for some time...do you have all the Shutdown patches installed?

I don't see why the computer would hang based on the settings I see, since your "custom" settings are even faster. Maybe something else is getting changed that we can't see...???

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 07/17/2004 09:42 AM
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Charlie22911
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it only does this when i change the ras to cas delay to 2,and my ram is cl2 so whats up with that? or are we talking about something different...
i haven installed the paches,i will give it a whirl (i thought it was strange,its never done that before,just started this week)


Charlie.

-------------------------
Desktop:
Phenom II x6 1055T @ 4GHz | 4x2GB Patriot DDR3 1600 @ 2000 | 3x AMD Radeon HD6970 Crossfire

Laptop:
Core i7 2960xm @ 4.2Ghz | 4x4GB Kingston DDR3 1866 | 2x GTX 580m SLI OC 725/1450/1500
 07/17/2004 01:03 PM
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KachiWachi
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You are confusing terms here.

The CAS Latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks.

So yes, both your sticks are CL2, but only if you clock them at 100MHz or less. If you clock them at 101-133MHz, they become CL3. This is determined from a chart in the chip datasheet.

For example, for your Micron MT 48LC16M8A2TG-75E, the -75 determines the CL rating of the part.

RAS to CAS delay is the amount of delay, in clocks, required between the Row Address Strobe and the Column Address Strobe. This is also determined from the chip datasheet.

The required minimum delay for your parts is 20nS. At 100MHz, this means you need 2 clocks to satisfy this requirement (1/100,000,000 = 10nS per clock x 2 = 20nS).

Same goes for the RAS Precharge Time...20nS minimum, so 2 clocks required.

So we can now say that you can set these parameters -

CAS Latency-2
RAS to CAS Delay-2
RAS Precharge Time-2

The other three parameters are a little harder to figure out, so I will get back to you with those.

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 07/17/2004 04:01 PM
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-Milt-
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@ KachiWachi,

Here's a couple of links to explanations of what those different settings mean, and do...
http://arstechnica.com/guide/building/bios/bios-1.html' ">http://arstechnica.com/guide/building/bios/bios-1.html
http://www.rojakpot.com/default.aspx?location=1' ">http://www.rojakpot.com/default.aspx?location=1

My own experience with the manufacturers 'CL2' or 'CL3' ratings leads me to believe that they should be taken with a large BAG of salt.
As one extreme example, I have an old 64 meg stick of 'PNY Electronics' SDRAM here that Sandra 'reads' as "(CL3 upto 100MHz )(CL2 upto 83MHz)"
So, in theory, this stick should 'max out' at 100 MHz, CL3, with relaxed memory timings.
Here's a shot of it (Memory Module 2), at 150 MHz, and I have had this stick up to 166.6 MHz!


-------------------------
Here is my new PCChips M848A' ">http://img.photobucket.com/alb...2_T-2-3-3-6-2_M848.jpg v2.1, with a 1700+ @ 2411 MHz, and my trusty old PCChips M810L' ">http://members.lycos.co.uk/mmm...00MHz_Sandra_tests.jpg v7.1A, with a Barton 2500+ @ over 3500+. Some of my fancy cars are on this pag
 07/17/2004 04:19 PM
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KachiWachi
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Refresh Command Delay and Refresh Queue Depth are related functions.

I found this -

Refresh Interval (15.6 µsec) -

Because capacitors are leaky, it is necessary to restore their content in 64 msec intervals, as defined by JEDEC standards. The refresh works by reading the data into the sense amps and then, without outputting them, moving them back into the memory cells. A typical memory chip contains 4k or 8k rows (4096 or 8192 rows). Opening a row will allow to refresh all cells within this row simultaneously. However, this also causes increased power consumption. This means that the best scheme for refreshing is not to refresh all rows at a time but to use an alternate refresh protocol, meaning that the best way to distribute the individual refreshes is to divide the 64 msec by the number of rows:

64000 µsec / 4096 = 15.6 µs

Consequently, a refresh command needs to occur every 15.6 µsec to service a single row. If there are more than 4k rows / chip, either 2 rows can be serviced with each command, or else, the refresh frequency needs to be doubled. Some BIOS offer the possibility to select the refresh frequency in µsec intervals. As a rule of thumb, for all current DIMMs the longest value of 15.6 µsec is adequate. As SDRAM densities will increase towards 1 GB / DIMM, it will become necessary to shorten the refresh interval since more address lines will need to be served.


DRAM Refresh Queue (1-8 Level) -

DRAM needs to be refreshed at a certain interval and this can be done one row at a time or in a queued manner in which a certain number of rows are refreshed in burst mode. Depending on which level is specified, up to 8 rows (pages) are refreshed sequentially.


So the Command Delay is how many clock cycles pass before a Memory Refresh Command is initiated, and the Queue Depth is how many rows are refreshed at that time.

For your Command Delay then, a larger number is actually better, since more clock cycles go by before a refresh (wasted cycle) is initiated. You can see this by the fact that for Best Performance, the default number is 8, while for Optimal, it is 6. Note that if you don't meet the 15.6uS refresh interval, you could lose data.

For your Queue Depth, again, higher numbers are better. Both settings use 12, so they are refreshing 12 rows in burst mode.

Try these settings then...see if your memory scores improve.

Refresh Command Delay-8 or 9
Refresh Queue Depth-12

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 07/17/2004 04:30 PM
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-Milt-
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@ KachiWachi

I found this, but it only seems to apply to memory sticks larger than 128 meg...
QUOTE Refresh Interval/Refresh Mode Select
Options : 7.8 µsec, 15.6 µsec, 31.2 µsec, 64 µsec, 128 µsec
Normally SDRAM and DDR are refreshed every 64ms. However, refreshing every cell simultaneously will result in a power surge. That's not good. So the refreshes can be staggered from one row to the next. 128Mbit and smaller DRAMs like to have this at 15.6 microseconds. 256Mbit DRAMs have twice the rows, so half the interval, 7.8 microseconds, is appropriate.

The JEDEC standards do call for 64ms (not µsec! but today's DRAM can handle more than that between refreshes, so for performance and power (mobile users listen well) reasons, you may want to increase this all the way to 128 microseconds to add a small delay on top of the 64ms already. It helps performance by keeping RAM available for longer. It helps power usage by not refreshing as often.

I think I just might try that on my M810L and see what it does for the low memory benches that it is notorious for... I've already messed with everything else!

-------------------------
Here is my new PCChips M848A' ">http://img.photobucket.com/alb...2_T-2-3-3-6-2_M848.jpg v2.1, with a 1700+ @ 2411 MHz, and my trusty old PCChips M810L' ">http://members.lycos.co.uk/mmm...00MHz_Sandra_tests.jpg v7.1A, with a Barton 2500+ @ over 3500+. Some of my fancy cars are on this pag
 07/17/2004 04:31 PM
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KachiWachi
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@ -Milt-

I hear you on the CL thing.

Note also your sticks have other numbers... PC133U-333-542 and PC100-322-622. The extra numbers are timing related... like the old DRAM Burst numbers (x222, x333, x322 etc...).

It comes down to looking at what the chips actually are on the module, and what the data sheets say they can do. As with overclocking, some parts come out better, and you can take advantage of that. Some don't, so you are stuck with what the spec says.

Sometimes a manufacturer will get a good deal on better parts, and just put them on modules they rate as slower, without reprogramming the SPD. So again, it's a crapshoot...sometimes you get better than what you pay for.

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 07/17/2004 04:41 PM
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Charlie22911
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when i loaded best preformance settings all i did was change the "ras to cas dealy" option back to 3 and she booted up like a charge,but i also notice an improvement,i will rin sandra tests and get back to you.

p.s. how do you like the imoticons that a couple of us at amd fourms raided:


Charlie.

-------------------------
Desktop:
Phenom II x6 1055T @ 4GHz | 4x2GB Patriot DDR3 1600 @ 2000 | 3x AMD Radeon HD6970 Crossfire

Laptop:
Core i7 2960xm @ 4.2Ghz | 4x4GB Kingston DDR3 1866 | 2x GTX 580m SLI OC 725/1450/1500
 07/17/2004 05:02 PM
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KachiWachi
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Interesting...

I just noticed that your EliteMT chip is a -8. My data sheet is for a -6 and -7, with the RAS-CAS Delay being 18 and 20 nS, respectively. I bet the -8 is an older part...maybe 22nS...so that would mean you need to set that to a "3".

You can verify that by testing each module seperately, and seeing if the EliteMT module dies when set to "2".



You shouldn't "borrow" images...lol!!


-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 07/17/2004 05:15 PM
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Charlie22911
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AHHAHAHA!where did you get those ?!
i have tried the 2 setting individually already,same result with each of them...
i will post my results but caught up in an article that -milt- posted about what burning in relay does in another topic...


Charlie.

-------------------------
Desktop:
Phenom II x6 1055T @ 4GHz | 4x2GB Patriot DDR3 1600 @ 2000 | 3x AMD Radeon HD6970 Crossfire

Laptop:
Core i7 2960xm @ 4.2Ghz | 4x4GB Kingston DDR3 1866 | 2x GTX 580m SLI OC 725/1450/1500
 07/17/2004 05:53 PM
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Charlie22911
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why are they lower,that sure is a confueser....



Charlie.

-------------------------
Desktop:
Phenom II x6 1055T @ 4GHz | 4x2GB Patriot DDR3 1600 @ 2000 | 3x AMD Radeon HD6970 Crossfire

Laptop:
Core i7 2960xm @ 4.2Ghz | 4x4GB Kingston DDR3 1866 | 2x GTX 580m SLI OC 725/1450/1500
 07/17/2004 06:02 PM
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KachiWachi
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Are you still running the Memory Bus at 100MHz?

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 07/17/2004 06:19 PM
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-Milt-
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I think Charlie would refuse to run any slower than 100MHz, (unless he was given a very good reason for doing so)

Somebody please correct me if I'm out to lunch here, but if you take the last digit, or two digits if it's, say, '-75' and divide that number into 1000, you then get the 'rated' FSB that it's designed to run at... e.g.
1000 / 10 = 100 MHz
1000 / 9 = 111.1 MHz
1000 / 8 = 125 MHz
1000 / 7.5 = 133.3 MHz
1000 / 7 = 142.8 MHz
1000 / 6.5 = 153.8 MHz
1000 / 6 = 166.6 MHz
This only seems to work if there are one (or two) distinct, separate numbers, at the very end of the memory chips number system.


-------------------------
Here is my new PCChips M848A' ">http://img.photobucket.com/alb...2_T-2-3-3-6-2_M848.jpg v2.1, with a 1700+ @ 2411 MHz, and my trusty old PCChips M810L' ">http://members.lycos.co.uk/mmm...00MHz_Sandra_tests.jpg v7.1A, with a Barton 2500+ @ over 3500+. Some of my fancy cars are on this pag
 07/17/2004 06:33 PM
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KachiWachi
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-Milt- :

If you are refering to the -75 at the end of his chip, in this case that doesn't apply.

In this case, the part could be -8E, -75, -7E, or -6A.


0136 L-1 MT 48LC16M8A2TG-75E

0136 - Manufacturers Date Code, Week 36 of 2001
L-1 - (I don't know what this is)

MT - Micron Technology, Inc.
48LC - Low Power CMOS
16M8 – 4 Meg x 8 x 4 banks

• WRITE Recovery (tWR)
tWR = “2 CLK”1 A2

• Package/Pinout
Plastic Package – OCPL2
54-pin TSOP II (400 mil) TG

• Timing (Cycle Time)
10ns @ CL = 2 (PC100) -8E
7.5ns @ CL = 3 (PC133) -75
7.5ns @ CL = 2 (PC133) -7E
6.0ns @ CL=3 (x16 only) -6A

As for Initial Latency Timer, I'm beginning to think that this setting has to do with PCI Transactions, and not the Memory Sub-System.

Charlie - is the order (32, 24, 16, Off), or (Off, 32, 24, 16)?

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 07/17/2004 06:54 PM
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-Milt-
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KachiWachi,

I think you are correct about the 'Initial Latency Timer' refering to the PCI bus, and not the memory timings.

But on the 'number scheme' that I suggested above... it makes sense, and more or less matches with your 'spec-sheet' readings...
Where the 7.5ns @ CL = 2 (PC133) -7E gets a PC133 rating, but it's a CL2, meaning it can go faster than the CL3 of the 7.5ns @ CL = 3 (PC133) -75 part.

Much the same for the 10ns @ CL = 2 (PC100) -8E... yes, it's a PC100 rating, but the CL2, means it can go faster than 100 MHz, or run tighter timings at 100 MHz.




-------------------------
Here is my new PCChips M848A' ">http://img.photobucket.com/alb...2_T-2-3-3-6-2_M848.jpg v2.1, with a 1700+ @ 2411 MHz, and my trusty old PCChips M810L' ">http://members.lycos.co.uk/mmm...00MHz_Sandra_tests.jpg v7.1A, with a Barton 2500+ @ over 3500+. Some of my fancy cars are on this pag
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