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Topic Title: Write Allocation
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Created On: 10/25/2004 12:58 PM
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 10/25/2004 12:58 PM
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KachiWachi
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I've been experimenting as you know on my Amptron PM-7900 in preparation for overclocking my DFI to 75MHz. While doing so, I came upon some data that I had overlooked in the past.

With the Amptron and its i200 non-MMX CPU, both read and write times are about the same, when tested using CacheCHK, with all caches enabled.

All caches off, 75MHz bus -

Read: ~53.4 uS/KB
Write: 10.6 uS/KB
Main RAM Read: 20.8 MB/s
Main RAM Write: 104.2 MB/s
Effective Main RAM Read Access Time: 403 nS
Effective Main RAM Write Access Time: 80 nS

CPU cache off, Motherboard (L2) cache on, 75MHz bus -

Read: 17.5, 22.7 uS/KB
Write: 10.6 uS/KB
Read L2: 63.0 MB/s
Main RAM Read: 48.4 MB/s
Main RAM Write: 104.2 MB/s
Effective Main RAM Read Access Time: 173 nS
Effective Main RAM Write Access Time: 80 nS

CPU cache on, Motherboard (L2) cache off, 75MHz bus -

Read: 3.5, 11.5 uS/KB
Write: 10.5 uS/KB
Read L1: 299.1 MB/s
Main RAM Read: 96.0 MB/s
Main RAM Write: 104.3 MB/s
Effective Main RAM Read Access Time: 87 nS
Effective Main RAM Write Access Time: 80 nS

All caches on, 75MHz bus -

Read: 3.5, 6.5, 11.5 uS/KB
Write: 10.5 uS/KB
Read L1: 308.9 MB/s
Read L2: 168.1 MB/s
Main RAM Read: 96.0 MB/s
Main RAM Write: 104.3 MB/s
Effective Main RAM Read Access Time: 87 nS
Effective Main RAM Write Access Time: 80 nS

With the DFI and its K6-2/+ 450 (6x66MHz for 400MHz currently), the write times are much longer than the read times. I was wondering if this was due to Write Allocation, or some other peculiarity about the board, so I ran some more tests.

All caches off -

Read: ~44 uS/KB
Write: ~20 uS/KB
Main RAM Read: 25.0 MB/s
Main RAM Write: 55.5 MB/s
Effective Main RAM Read Access Time: 335 nS
Effective Main RAM Write Access Time: 151 nS

CPU cache off, Motherboard (L3) cache on -

Read: 19.9, 24.3 uS/KB
Write: ~20 uS/KB
Read L3: 55.5 MB/s
Main RAM Read: 45.2 MB/s
Main RAM Write: 55.5 MB/s
Effective Main RAM Read Access Time: 185 nS
Effective Main RAM Write Access Time: 151 nS

CPU cache on, Motherboard (L3) cache off -

Read: 0.7, 1.0, 6.5 uS/KB
Write: 0.7, 1.2, 13.5 uS/KB
Read L1: 1659.8 MB/s
Read L2: 1100.3 MB/s
Write L1: 1656.8 MB/s
Write L2: 921.8 MB/s
Effective Main RAM Main RAM Read: 168.7 MB/s
Effective Main RAM Main RAM Write: 81.6 MB/s
Read Access Time: 49 nS
Write Access Time: 102 nS

All caches on -

Read: 0.7, 1.0, 3.0, 6.5 uS/KB
Write: 0.7, 1.2, 6.8, 14.9 uS/KB
Read L1: 1659.8 MB/s
Read L2: 1108.9 MB/s
Read L3: 369.9 MB/s
Write L1: 1656.7 MB/s
Write L2: 922.1 MB/s
Write L3: 161.4 MB/s
Main RAM Read: 168.6 MB/s
Main RAM Write: 73.6 MB/s
Effective Main RAM Read Access Time: 49 nS
Effective Main RAM Write Access Time: 113 nS

Note that as soon as I enabled the motherboard cache, write times to Main RAM slowed down by about 11%. Also note that the overall write times are ~50% longer on the DFI...with no caches enabled!!!

I then went to turn off Write Allocation (my BIOS is patched to automatically enable it), but found that the DOS utilities that I had would not disable it.

So I'm stuck now for the moment, until I find a DOS tool to disable my WA. Any idea if the WA is responsible for the apparent slowdown in RAM write times, once all three caches are enabled?

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 10/25/2004 04:55 PM
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mcmab
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Remember that WA involves a 32-byte burst read cache line replacement.

I think you'll find that the 430VX only caches the lower 64MB of system memory though you have 128 EDO.

I found that with my 430TX that the optimal memory timings, using SDRAM, were not the minimum values. With SDRAM there is "speculative read ahead", i.e. after a location has been read the chipset sets the address lines to load the next memory location into the sense amps. When I increased the keep page open timer to 8 cycles my main memory bandwidth went from 110MB/sec to 200MB/sec (I think, I used to have Win98 with setk6 that reported bandwidth at startup - now I'm on Win 2000). Anyway INCREASING the keep page open bios setting dramatically improved both the benchmark and actual performance.

I put this down to optimizing the burst read cycle which was unique to the K6 series. Generic (i.e. intel) settings would not have taken this into account

You can use setk6 to turn WA on and off.

All my settings were on a 75MHz bus using a k6-III at 6x75

Cheers
 10/25/2004 05:45 PM
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KachiWachi
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Yes...a VX will only cache up to 64MB RAM, but CacheCHK only tests the lower 64MB so...

Speculative Leadoff Disable is off, and the VX guideline specifically states that if you have an L2 (Motherboard) cache, you should not enable it. (Actually, I think there was an Addendum that said you CANNOT enable it.)

I have SetK6D (DOS version), and it always displays that WA is disabled for me. Even when I tell it to turn WA on or off, the CPU MSR's do not change.

What is the "Keep Page Open" BIOS setting, or is that specific to the TX chipset? Do you know which Device Configuration Register that is?

The only difference between the Amptron and the DFI is that the Amptron has the Rev. 1 (SU085) System Controller, while the DFI has the Rev. 2 (SU116) version. They both have the same Revision (2) of the IDE Controller (SU093). Both are using the best RAM timings possible. (Actually, the Amptron can only run 3,6,3,x222,x222,1,FEDO ON,5 or 3,7,2,x222,x222,1,FEDO ON,5 timings at 66MHz (and 4,7,3,x222,x222,1,FEDO OFF,5 at 75MHz), where the DFI can run 3,6,2,x222,x222,1,FEDO ON,5.)

**Also of note is that I just found out that the same thing happened when my Cyrix MII was on-board...the write times were slower than the read times. I guess the only way to be sure is to put the i200 in the DFI and see what happens. This could be a difference in the chipset timing after all...

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 10/25/2004 08:29 PM
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mcmab
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Now you seriously owe me! This machine runs 24/7 and its the first time I've restarted in a week.

The setting I found that made a serious change to bandwidth is called "DRAM Page Idle Timer". Default I think is 3 or 4. Its optimal (for SDRAM on the k6) at 8 or 10.

I remember now. When set at default my bandwidth was ~150MB/sec. At 8 cycles it went to 213.7 MB/sec

My CAS latency is 2, memory timings at 10/6/3

EDO leadoff pullin is different, that shaves a cycle off of the setup time when the address lines are driven.

"Speculative SDRAM read ahead" is N/A I think on EDO.

I think what happens is that the K6 uses the cache line replacement cycle a lot. Its 4 back-to-back reads of 8 bytes. Optimally you want the northbridge to open the next memory page AND KEEP IT OPEN for the burst cycle. Take a look at the timing diagrams in the AMD docs. So for the second, third and fourth 8 byte reads the sense amps are already loaded with data - the memory/northbridge is actually operating in parallel with the processor.

Have you tried WPCREDIT to look at the registers? I'm sure Mr. Oda has a register file for the VX chipset.

In case you wonder, yes I have faster machines at my disposal. An XP-2600 is a few feet away. This little K6-3 (not so little, a big old AT box from 1991 but now with GeForce graphics + RAID) is totally reliable, runs cool and is faster than anyone can believe. Just a K6-III with 256MB PC-100 SDRAM but fast, fast disks.
 10/25/2004 10:34 PM
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KachiWachi
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LOL...my machine runs 24/7 as well...and it hasn't run DOS since I switched over to W2K full time in July!!

I don't have a "DRAM Page Idle Timer" BIOS setting, but I'll look to see if there is something similar in the VX.

I have the chipset document from Intel, so I know where all the registers are, and what they do. I use Craig Hart's PCI program to dump the chipset configuration registers to a text file, and Jan's ReadMSR program for the CPU registers.

Unfortunately, I didn't download the Chipset Specification Update until tonight (try finding that now on the Intel site...whew!!, so I'm looking at that now as I write this, to see if anything has changed between the two revisions.

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 10/26/2004 02:22 PM
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KachiWachi
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OK...

I was able to use CTCM to disable the WA. Here is the data -

CPU cache on, Motherboard (L3) cache off, WA off -

Read: 0.7, 1.0, 6.5 uS/KB
Write: 19.8 uS/KB
Read L1: 1662.4 MB/s
Read L2: 1113.7 MB/s
Main RAM Read: 168.7 MB/s
Main RAM Write: 55.5 MB/s
Effective Main RAM Read Access Time: 49 nS
Effective Main RAM Write Access Time: 151 nS

All caches on, WA off -

Read: 0.7, 1.0, 3.0, 6.5 uS/KB
Write: 19.8 uS/KB
Read L1: 1662.5 MB/s
Read L2: 1113.9 MB/s
Read L3: 370.0 MB/s
Main RAM Read: 168.7 MB/s
Main RAM Write: 55.5 MB/s
Effective Main RAM Read Access Time: 49 nS
Effective Main RAM Write Access Time: 151 nS

Note that with WA off, there is no Write Performance Data to the caches!! (Why??)

In order to compare apples to apples, here is the Amptron data at 66MHz -

All caches off, 66MHz bus -

Read: ~48 uS/KB
Write: 11.8 uS/KB
Main RAM Read: 23.1 MB/s
Main RAM Write: 92.9 MB/s
Effective Main RAM Read Access Time: 362 nS
Effective Main RAM Write Access Time: 90 nS

CPU cache off, Motherboard (L2) cache on, 66MHz bus -

Read: 19.6, 24.5 uS/KB
Write: 11.8 uS/KB
Read L2: 56.0 MB/s
Main RAM Read: 44.8 MB/s
Main RAM Write: 92.9 MB/s
Effective Main RAM Read Access Time: 187 nS
Effective Main RAM Write Access Time: 90 nS

CPU cache on, Motherboard (L2) cache off, 66MHz bus -

Read: 3.9, 11.8 uS/KB
Write: 11.8 uS/KB
Read L1: 267.6 MB/s
Main RAM Read: 92.9 MB/s
Main RAM Write: 92.9 MB/s
Effective Main RAM Read Access Time: 90 nS
Effective Main RAM Write Access Time: 90 nS

All caches on, 66MHz bus -

Read: 3.9, 7.4, 11.8 uS/KB
Write: 11.8 uS/KB
Read L1: 274.5 MB/s
Read L2: 149.4 MB/s
Main RAM Read: 92.9 MB/s
Main RAM Write: 92.9 MB/s
Effective Main RAM Read Access Time: 90 nS
Effective Main RAM Write Access Time: 90 nS

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 10/27/2004 09:42 AM
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KachiWachi
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I found out what the "DRAM Page Idle Timer" does.

From -> http://www.oempcworld.com/supp...Tech...Perspective.htm' ">http://www.oempcworld.com/supp...hnical_Perspective.htm

"Frequently a fourth parameter is referred to as the "DRAM Idle Timer" in the BIOS. This is also known as the RAS cycle time (tRC). In the PC100 SDRAM specification this has a maximal value of 8. In an alternate notation, 3-2-2 modules with a tRC of 8 are referred to as 3/2/2/8. The minimum standard for PC100 SDRAM is 3/3/3/8."

For me and my 60nS EDO RAM, tRC is 104nS Minimum, which, at 66MHz, equates to 7 clock cycles, or the "DRAM R/W Leadoff Timing" setting.

The DFI must have slightly better RAM than the Amptron, since I can use the 6 (90nS) setting there, which puts them closer to 50nS EDO (84nS tRC). The Amptron will not boot if I use the 6 setting, unless I increase the "Fast RAS to CAS Delay" setting (tRCD) from 2 to 3. tRCD is specified as 14-45nS for the RAM, with this equating to 30ns (2 clocks) and 45nS (3 clocks) at 66MHz. However, there is a note in the spec which indicates that tRCD can exceed its Maximum value (it is given as Reference Only), with access time then being controlled by tCAC (15ns Minimum).

So I'm playing with a few things here to see what happens.

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 10/28/2004 03:58 PM
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Ken B.
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Hey guys,

I was trying to see if the write allocate feature is turned on or off on my board, and in looking around for info about it found this thread. Unfortunately, you guys are talking way over my head, so I'll make my humble request brief.

How can I find out in Windows2000 if the write allocate feature is on or off on my K6-2+ 550? I have it mounted in a Soyo 5EMA+ (VIA MVP3 chipset), and my board BIOS does not have such a feature listed. I have Sisoft Sandra 2004, if that is any help.

Finally, how are you guys getting figure like 200MB/s or whatever? And on an old VX chipset? I've tried tweaking my BIOS to the max ("Turbo" settings, no ECC, memory interleave enabled, CAS 2, and the like) and I'm still getting only about a max of 169MB/s or lower on my memory bandwidth benchmarks, according to Sandra. I'm using PC100 Micron SDRAM at 100Mhz and my board has 1MB cache.

Any other tips to increase my memory or CPU speed without introducing instability?

Thanks for your time!

-Ken


 10/28/2004 04:08 PM
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Ken B.
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Also guys, I found this on Anandtech...is this feature available somehow?

"Where Write Allocate fails, the K6-2's (Model 8/[F:8]) 8-byte Write Merge Buffer picks up. Instead of simply leaving non-cacheable write cycles alone, the Write Merge Buffer combines the data segments from all a group of memory writes into this 8-byte buffer. By combining all of the writes into the Write Merge Buffer, you can theoretically reduce processor bus utilization and processor stalls, which accounts for the overall increase in performance the newer F:8 stepping offers over the older processors.

How can you take advantage of the improvements found in the new CXT core? Unfortunately it isn't as simple as popping in a new chip, you will have to make an update to your BIOS to recognize the processor as well as to enable the enhanced WHCR and the Write Merge Buffer. As you'll be able to see from the tests AnandTech conducted, the K6-2 400 using the CXT core exhibited a 7% increase in overall performance in comparison to a K6-2 400 without the modifications enabled in the WHCR and with the Write Merge Buffer."

 10/28/2004 04:45 PM
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KachiWachi
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You can find out the state of your CPU by looking at the MSR's. This will tell you if the CPU is set up properly for Write Allocation, and Write Ordering. I use Jan's ReadMSR program for this, run from a DOS boot floppy.

All of my data is also taken in DOS, using CacheChk. I find personally that data taken in Windows can change due to whatever you have running at the time...so I eliminate that. But just for reference, I took these numbers earlier (but forgot to report them ) -

AIDA32 RAM Test Data -

With Motherboard L3 on, WA on -
Read = 155MB/s
Write = 73MB/s

With Motherboard L3 off, WA on -
Read = 158MB/s
Write = 79MB/s

To check/set these while in W2K, you need to download K6Speed from here ->

http://www.k6plus.com/modules....odlo...wdownload&cid=1' ">http://www.k6plus.com/modules....req=viewdownload&cid=1

Don't forget to get the v.88 update as well!!

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 10/28/2004 11:30 PM
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Ken B.
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But how are you guys getting figure like 200MB/s or whatever? And on an old VX chipset?
 10/29/2004 07:27 AM
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KachiWachi
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I'm only getting ~170MB/s (reading) with 60nS EDO SIMMS...

I mention my RAM settings above. What motherboard do you have?

I do have some compatible PC-66 DIMMS here that I can put in the test bed and try, though I'm going to guess that I won't be able to OC them very much...

Keep in mind that this thread is about why my one VX board does not have the "write speed" that my other one does...but I will grant some lattitude...

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 10/29/2004 11:47 AM
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Ken B.
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Ok, Kachi. Then we're about even. My Soyo 5EMA+ board is giving me 169MB/s with all memory settings at max.

By the way, I downloaded the K6Speed util you mentioned, but it fails to initialize and terminates. Any ideas? I'm using Win2K.

Thanks.
 10/29/2004 03:41 PM
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KachiWachi
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And that's a good thing??

Your machine is capable of a 100MHz bus and more. I'm running with a 66MHz bus...you should be doing alot better than matching what I have going on...

Ever try stepping on that board a bit to see what it will do?

No clue as to why K6Speed didn't initialize properly. Did you get the v.88 update?? What CPU do you have installed?

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 10/29/2004 04:22 PM
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Ken B.
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I have a K6-II+ 550Mhz.

Also, the v.88 update is what I downloaded. But it says "Failed to initialize" or something. This is on a relatively fresh Win2000 install and stress testing, so there's no issues with the system.

Weird.

Should I even bother?
 10/29/2004 04:42 PM
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eddaweaver
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have you turned ECC off? That slows things down
 10/29/2004 05:52 PM
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KachiWachi
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Did you also download the v.87 package?

You need both, since the companion .SYS and .VXD are in that package, and are required to hook the OS.

Just replace the v.87 .EXE with the v.88 one and all should be fine.

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 10/29/2004 07:07 PM
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mcmab
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213MB/sec at 75MHz bus speed on a 430TX is my read speed.

Read what I said above, setting all at "MAX" is not optimal. I presume you mean the lowest setting by "MAX".

You need to optimize for the 4x8 byte read bus timing. In the case of SDRAM here's how I get 213MB/sec:

1st 8 bytes are read normally
2nd THEN: chipset (not the k6) advances the address lines to next higher 8-byte location (speculative read)
3rd NOW: DRAM page idle timer is long enough that the sense amps have the data AND HOLD IT UNTIL:
4th K6 reads the next 8 bytes

then repeat steps 2-4 two more times. If the DRAM page idle times is too short the data in the sense amps will be invalidated and there will be a holdoff until it is read again.

This mistake is to think all bios memory setting should be short to be optimal. That is not true. You have to play around to find the best settings and the best settings for the k6 are NOT the same as that for an intel chip as they use the bus in a different way.
 11/01/2004 08:51 AM
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KachiWachi
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It also has to do with what settings are available in the BIOS (hidden or otherwise), and what the System Chipset itself can deliver.

Motherboard component layout can also have an effect on what timings you can get away with (trace length, etc...).

RAM chips need certain timings to work properly...if the clock duration (BIOS setting vs. part requirement) isn't long enough, you will get errors...too long, and you are wasting time. The component datasheet will provide you with the required specifications for the part. Some parts in the batch may be better than advertised...especially if they came in various speed grades...this is a good thing.

Don't forget that your Motherboard (L2) cache (TAG and SRAM) is also part of the equation.

mcmab - What tool do you use to determine your timings?

-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
 11/03/2004 08:12 AM
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KachiWachi
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I got an e-mail from Jan, and he said he'd look into this a bit.

Just for comparison, I ran the DFI at the 3,6,3 settings. In summary, I lost 0.3uS/KB, 6MB/s, and 2nS (reading), and 0.8uS/KB, 3.3MB/s, and 7nS (writing). With WA off, I got the same changes as above (reading), and no changes (writing).

All caches on, WA on, 3,6,3 timings -

Read: 0.7, 1.0, 3.0, 6.8 uS/KB
Write: 0.7, 1.2, 6.8, 15.7 uS/KB
Read L1: 1659.8 MB/s
Read L2: 1108.9 MB/s
Read L3: 369.8 MB/s
Write L1: 1656.7 MB/s
Write L2: 922.1 MB/s
Write L3: 161.4 MB/s
Main RAM Read: 162.6 MB/s
Main RAM Write: 70.1 MB/s
Effective Main RAM Read Access Time: 51 nS
Effective Main RAM Write Access Time: 120 nS

Also note that Speculative Write Ordering has been set to the "slowest" setting (Strong Write Ordering enforced) throughout all of these tests.

I have also swiched the Refresh RAS# Assertion back to 4 clocks, since this is the proper setting for the currently installed RAM. There is no (measureable) change in performance due to this change.


-------------------------
KachiWachi

Moderator - Wim's BIOS

CPU #1 - DFI 586IPVG, K6-2/+ 450 (Cyrix MII 433), 128MB EDO. BIOS patched by Jan Steunebrink.
CPU #2 - Amptron PM-7900 (M520), i200 non-MMX, 128MB EDO
CPU #3 - HP8766C, PIII-667, 768MB SDRAM
CPU #4 - ASUS P3V4X, PIII-733, 256MB SDRAM
CPU #5 - ??? ;)
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