How fast would a 64,128 or 192 bit parallel bus be, with the switching speed of the SATA 3 chips, if it had chips of the same switching speeds set up to work in a parallel format? I wonder if you would use RAM type slots to plug them into?
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If it were fast enough, and set up with volatile and non-volatile modes as needed, could you eliminate the RAM?
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ASUS M5A99X EVO, AMD FX 8 Core Black Edition, 8 Gig DDR3 1333, 2 EA. GeForce GTS450 in SLI Cofiguration, 120 Gig Intel SSD, Thermal take Smart M Series 850 Watt Power Supply, and 14 TByte internal storage.
I am not suggesting using SATA 3 (Serial) busses. The Question is if a solid state hard drive had 3 64 bit parallel busses, where the chips had the switching speeds of the current SATA 3 chips, how fast would it go?
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Mime Forum Moderator
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Parallel busses have a higher chance of crosstalk, so they're harder to scale than serial busses. That's one reason why many of the older parallel busses like PCI and PATA were replaced with PCI Express and SATA which are both(mostly) serial. A faster clocked serial bus can often get you the same or more bandwidth with lower latency due to its higher clock speed.
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Do not meddle in the affairs of archers, for they are subtle and quick to anger. Post Count: +8510 Troll Hunter
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Been there, done that. Parallel communication does, in fact, let you send more bits per signal. If your signal rate is limited, it's the obvious way to get more data sent per signal interval. But keeping multiple bits per signal in sync is not trivial. Parallel SCSI is the best example to explore this model.
The original SCSI, in 1986, had a signal rate of 5MHz, and sent 8 bits per signal. That allows SCSI-1 devices to transfer data at 40Mbps (5MB/sec). Fast SCSI (AKA SCSI-2) doubled the signal rate to 10MHz, making the transfer tate 80Mbps. Fast-Wide SCSI, introduced in 1996, doubled the number of bits per signal to 16, bringing us up to 160Mbps. Then there was Ultra SCSI, which had a signal rate of 20MHz, with both narrow and wide versions (160Mbps and 320Mbps, respectively). The latest parallel SCSI spec (Ultra-640 from 2003) has a 160MHz signal rate and 16 bits per signal, for a 5Gbps data rate.
Notice something about that progression? The number of bits per signal never got above 16. Why not? Because it would be too difficult to keep all the bits in sync and error free.
Creating very high signal rates had been getting easier and easier, and it's much simpler to send a single bit a few billion times per second than a larger number of bits less frequently. That concept had already been well tested with fiber optic signalling (IBM's SSA and then the standard Fibre Channel). So parallel ATA gave way to SATA, and parallel SCSI gave way to SAS. And since ATA devices were becoming steadily more like SCSI at the command level, SATA is actually a subset of SAS - you can connect SATA drives to SAS ports and controllers (but not the other way around).
It's conceivable that in the future, we'll hit a wall with signalling rates, and going parallel will be the best option for increasing speed. But I don't find it terribly likely. A high signalling rate only exacerbates the problems associated with handling multiple bits per signal.
I Believe in an earlier topic I asked the question as to what effect path lengths would have on how fast a bus could run. Equal length paths of the same 3 dimensional dimensions, length, width & thickness, would have the same amount of resistance, capacitance & inductance which affects the shape of a clock or data pulse & timing of parallel lines. Also the shorter the paths are reduces the resistance and crosstalk.
Say for instance you plug the processor into a memory bank, let's not call it a hard drive, and plug the memory bank into the motherboard.
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black_zion Heavy Wizardry
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I believe you are describing a "diskless" system, something which has been around for many many years, most commonly used in parallel processing group node systems and servers where there is a "master" system with actual drives and the "slaves" load everything into a RAM Disk style system
Mime Forum Moderator
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Even then, those terminals usually have some kind of scratch space that they treat like a hard drive. Whether it's local to that machine or not depends on the performance requirements for each terminal.
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Do not meddle in the affairs of archers, for they are subtle and quick to anger. Post Count: +8510 Troll Hunter
The opinions expressed above do not represent those of Advanced Micro Devices or any of their affiliates.
I am not familiar with that system. My question is if one uses a solid state parallel bus memory bank, along with corrections to the pathways that affect timing, how fast could the parallel bus go before it started dropping bits?
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Mime Forum Moderator
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It's still a bad idea. You can't eliminate crosstalk just by making all the bus lines the same length.
It's like road trips, with kids involved. The longer the kids are confined to the car, the more cranky they become... and the more kids there are, the worse things will be. Traveling an hour with two kids in the car isn't a huge deal, but if you change that to 16 kids traveling for 8 hours you've got something that will cause mere mortals to want to hang themselves in the shower.
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Do not meddle in the affairs of archers, for they are subtle and quick to anger. Post Count: +8510 Troll Hunter
The opinions expressed above do not represent those of Advanced Micro Devices or any of their affiliates.
It is the length of the lines that that effects crosstalk, the shorter the paths the less the charging and collapsing magnetic fields can affect it's neighbors. The paths being of equal length effects timing. In high speed switching a path that is a 1/16 of an inch longer than the rest will slow down how fast the system can run.
P.S.
I Liked your analogy!
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black_zion Heavy Wizardry
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It's also why the megaspeed interconnects (OC class, the kind that cross oceans and such) rely on atomic clocks to keep everything synced, internal clock generators aren't accurate enough. By the time things need to go that fast inside a computer system the technology will change so it is able to do more with less, same reason we don't have 250x speed optical drives, new laser technology.
Mime Forum Moderator
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It's the length of the lines in total that matters when dealing with crosstalk...not the length relative to each other. Dealing with timing is a different issue.
Timing and clock skew are things engineers have worked with almost since we started creating integrated circuits, so it's not like this is a new problem.
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Do not meddle in the affairs of archers, for they are subtle and quick to anger. Post Count: +8510 Troll Hunter
The opinions expressed above do not represent those of Advanced Micro Devices or any of their affiliates.
In gaming isn't faster better, more frames per second!
Oh no, not clock skew! AHHHHHHHH!
Yes the further a device is away from the clock the more time delay on the clock pulse. but if the clock pulse and address/data bus lines are of the same length the they should all have the same time delay.
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Mime Forum Moderator
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There's no magic bullet here dude...
Clock skew can still happen even if all your wires are the same physical length. A clock signal can often take longer to propagate through one configuration of logic gates than another... leading to clock skew. Temperature variations and impurities in materials can cause it also.
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Do not meddle in the affairs of archers, for they are subtle and quick to anger. Post Count: +8510 Troll Hunter
The opinions expressed above do not represent those of Advanced Micro Devices or any of their affiliates.
I agree there is a speed limit, but what is the speed limit?
Oh NOOOOOO Not clock cops! The fine is craaaaaaash.
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12/07/2012 08:34 AM
